1. Field of the Invention
The present invention relates to a semiconductor device packaging substrate and a semiconductor device packaging structure, and more particularly, a semiconductor device packaging substrate and a semiconductor device packaging structure in which an underfill resin is filled between the packaging substrate and a semiconductor device mounted to the packaging substrate in flip-chip bonding.
2. Description of the Related Art
As a method of packaging a semiconductor device which is high in density onto a packaging substrate, flip-chip bonding is used frequently. According to this flip-chip bonding, the semiconductor device is mounted by providing solder bumps on the bottom surface of the semiconductor device as external connection terminals, then setting this semiconductor device in a face-down state to the packaging substrate, and then bonding the solder bumps to electrodes formed on the packaging substrate.
FIG. 1 shows an example of a packaging substrate 1 on which a semiconductor device (semiconductor element) 5 is mounted by the flip-chip bonding in the related art. In FIG. 1, an example in which the semiconductor device 5, such as DRAM, having a center pad structure is mounted on the packaging substrate 1 is shown.
The packaging substrate 1 is a printed-wiring board, and predetermined wiring patterns, electrodes, etc. are formed on its surface. Also, a solder resist 2 for protecting the wiring patterns, the electrodes, etc. is provided on the surface of the packaging substrate 1.
The solder resist 2 is a resin that has insulating performance and also has a function of preventing adhesion of the solder. An opening portion 3 is formed in a portion, in which the electrodes to be bonded to the solder bumps formed on the semiconductor device 5 are formed, of a packaging area 6 of the solder resist 2, in which the semiconductor device 5 is mounted. Therefore, the electrodes (not shown) bonded to the bumps formed on the packaging substrate 1 are exposed to the outside via the opening portion 3.
In the meanwhile, in a case where a difference in thermal expansion between the packaging substrate 1 and the semiconductor device 5 is large, a stress caused due to such difference in thermal expansion in heating is applied to the solder bumps when the semiconductor device 5 is flip-chip bonded to the packaging substrate 1. Thus, a problem arises in packaging reliability. Therefore, in the related art, a stress caused due to a difference in thermal expansion is suppressed by providing an underfill resin 7 between the semiconductor device 5 and the packaging substrate 1 after the semiconductor device 5 is flip-chip mounted on the packaging substrate 1, and thus the packaging reliability is improved (see JP-A-2002-329744, for example).
FIG. 2 is a plan view showing a process of providing the underfill resin 7 between the packaging substrate 1 and the semiconductor device 5. Because the underfill resin 7 is provided between the packaging substrate 1 and the semiconductor device 5, illustration of the semiconductor device 5 is omitted herein and only its packaging area 6 is illustrated, for convenience of illustration.
In order to provide the underfill resin 7, a liquid underfill resin 7 is injected between the packaging substrate 1 and the semiconductor device 5 from an injection starting position 9. In an example shown in FIG. 2, the injection starting position 9 is set in a position of the bottom portion of the opening portion 3 in FIG. 2. The underfill resin 7 when injected from the injection starting position 9 flows upward in FIG. 2 to spread into a space between the packaging substrate 1 and the semiconductor device 5.
In this injection, a flow end surface 7A as a top end portion of the underfill resin 7 is not formed as a linear end but a curved end shown in FIG. 2. This is caused due to the fact that a flow speed of the liquid underfill resin 7 in areas that are located along edge portions 3A of the opening portion 3 and outer peripheral portions 6A of the semiconductor device 5 is higher than that in other areas. More concretely, a flow speed V2 at the edge portion 3A and a flow speed V3 at the outer peripheral portion 6A is higher than a flow speed of the underfill resin 7 on the solder resist 2 indicated with an arrow V1 in FIG. 2 (V1<V2, V1<V3).
Also, FIG. 4 shows an example in which two opening portions 3, 4 are formed in the solder resist 2 to mount the semiconductor device having the pad structure in two rows. As shown in FIG. 4, when the opening portions 3, 4 are formed in parallel and then the underfill resin 7 is injected in the direction that is perpendicular to the opening portions 3, 4, particularly the underfill resin 7 goes around fast conspicuously.
In this manner, a flow speed of the underfill resin 7 is not uniform on the packaging substrate 1, nevertheless this problem was not handled properly in the related art. For this reason, a curved shape of the flow end surface 7A becomes prominent based on a difference in speed when the underfill resin 7 flows from the injection starting position 9 to the opposite side. Then, because the portion of the underfill resin 7 whose flow speed is fast flows to go around the portion whose flow speed is slow, voids 8 are generated in the inside of the underfill resin 7 under certain circumstances, as shown in FIG. 3 and FIG. 5.
FIG. 6A shows an SAT (Scanning Acoustic Tomography) image in which voids 8 are generated in the inside of the underfill resin 7 when the underfill resin 7 is injected between the packaging substrate 1 and the semiconductor device 5 as the first related art. FIG. 6B shows an image when surface grinding is performed in the state shown in FIG. 6A.
FIG. 6C is a cross-sectional view of a semiconductor device packaging structure along the line A-A′ of FIG. 6A. In this case, an Au stud bump 11 formed on the semiconductor device 5 and a substrate conductor (electrode) 13 formed on the packaging substrate 1 is connected via a solder 12. In FIG. 6C, voids are not generated.
FIG. 6D is a cross-sectional view of the semiconductor device packaging structure along the line B-B′ of FIG. 6A. In this case, the void 8 is generated in the inside of the underfill resin 7 around the solder 12 between the semiconductor device 5 and the packaging substrate 1.
FIG. 6E is a cross-sectional view of the semiconductor device packaging structure along the line C-C′ of FIG. 6A. In this case, the void 8 is generated in the inside of the underfill resin 7 above the packaging substrate 1 between the semiconductor device 5 and the packaging substrate 1.
In this manner, in case the voids 8 are generated in the inside of the underfill resin 7, it is possible that an air in the voids 8 is expanded by the later heating resulting a breakage of the underfill resin 7, or the underfill resin 7 cannot sufficiently absorb a stress caused between the packaging substrate 1 and the semiconductor device 5. Thus, such a problem is caused that the packaging reliability is deteriorated.